library ieee;
use ieee.std_logic_1164.all;

entity testbench_ffd is
end testbench_ffd;

architecture test of testbench_ffd is

	component ffd
		port (
			d_i     : in  std_logic;
			set_i   : in  std_logic;
			reset_i : in  std_logic;
			nclk_i  : in  std_logic;
			q_o     : out std_logic
		); 
	end component;

	signal d     : std_logic;
	signal set   : std_logic;
	signal reset : std_logic;
	signal nclk  : std_logic;
	signal q     : std_logic;

begin

	ffd_inst : ffd port map (
		d_i     => d,
		set_i   => set,
		reset_i => reset,
		nclk_i  => nclk,
		q_o     => q
	); 

	gen_clk : process
	begin
		nclk <= '0';
		wait for 10 ns;
		nclk <= '1';
		wait for 10 ns;
	end process;

	gen_test : process
	begin
		wait for 100 ns;

		d     <= '0';
		set   <= '0';
		reset <= '1';

		wait for 30 ns;

		d     <= '0';
		set   <= '1';
		reset <= '0';

		wait for 30 ns;
		
		d     <= '1';
		set   <= '0';
		reset <= '0';
		
		wait for 30 ns;
		
		d     <= '0';
		set   <= '0';
		reset <= '0';

		wait for 30 ns;

		d     <= '0';
		set   <= '1';
		reset <= '0';

		wait;
	end process;

end test;
